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high voltage, fractional-n/ integer-n pll synthesizer adf4150hv rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features fractional-n synthesizer and integer-n synthesizer high voltage charge pump: v p = 6 v to 30 v tuning range: 1.0 v to 29 v (or 1 v from v p supply rails) rf bandwidth to 3.0 ghz programmable divide-by-1/-2/-4/-8/-16 outputs synthesizer power supply: 3.0 v to 3.6 v programmable dual-modulus prescaler of 4/5 or 8/9 programmable output power level programmable charge pump currents rf output mute function 3-wire serial interface analog and digital lock detect applications wireless infrastructure microwave point-to-point/point-to-multipoint radios vsat radios test equipment private land mobile radios general description the adf4150hv is a 3.0 ghz, fractional-n or integer-n frequency synthesizer with an integrated high voltage charge pump. the synthesizer can be used to drive external wideband vcos directly, eliminating the need for operational amplifiers to achieve higher tuning voltages. this simplifies design and reduces cost while improving phase noise, in contrast to active filter topologies, which tend to degrade phase noise compared to passive filter topologies. the vco frequency can be divided by 1, 2, 4, 8, or 16 to allow the user to generate rf output frequencies as low as 31.25 mhz. for applications that require isolation, the rf output stage can be muted. the mute function is both pin- and software-controllable. a simple 3-wire interface controls all on-chip registers. the charge pump operates from a power supply ranging from 6 v to 30 v, whereas the rest of the device operates from 3.0 v to 3.6 v. the adf4150hv can be powered down when not in use. functional block diagram muxout cp out ld ref in clk data le av dd sdv dd dv dd v p gnd ce cp gnd sd gnd r set rf out + rf out ? rf in + rf in ? phase comparator high voltage charge pump output stage rf input pdb rf multiplexer 10-bit r counter 2 divider 2 doubler function latch data register integer value n counter fraction value third-order fractional interpolator modulus value multiplexer lock detect adf4150hv divide-by-1/ -2/-4/-8/-16 current setting boost mode 09058-001 figure 1.
adf4150hv rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 6 ? transistor count ........................................................................... 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 9 ? circuit description ......................................................................... 11 ? reference input section ............................................................. 11 ? rf n divider ............................................................................... 11 ? phase frequency detector (pfd) and high voltage charge pump .............................................................................. 11 ? muxout and lock detect ...................................................... 12 ? input shift registers ................................................................... 12 ? program modes .......................................................................... 12 ? output stage ................................................................................ 12 ? register maps .................................................................................. 13 ? register 0 ..................................................................................... 17 ? register 1 ..................................................................................... 17 ? register 2 ..................................................................................... 17 ? register 3 ..................................................................................... 19 ? register 4 ..................................................................................... 19 ? register 5 ..................................................................................... 19 ? register initialization sequence ............................................... 19 ? rf synthesizera worked example ...................................... 20 ? reference doubler and reference divider ............................. 20 ? 12-bit programmable modulus ................................................ 20 ? spurious optimization and boost mode ................................ 21 ? spur mechanisms ....................................................................... 21 ? spur consistency and fractional spur optimization ........... 21 ? phase resync ............................................................................... 22 ? applications information .............................................................. 23 ? ultrawideband pll .................................................................... 23 ? microwave pll ........................................................................... 23 ? generating the high voltage supply ....................................... 24 ? interfacing to the aduc702x and the adsp-bf527 ............. 25 ? pcb design guidelines for a chip scale package ................. 25 ? output matching ........................................................................ 26 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 27 ? revision history 8/11revision 0: initial version
adf4150hv rev. 0 | page 3 of 28 specifications av dd = dv dd = sdv dd = 3.3 v 10%; v p = 6.0 v to 30 v; gnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85c. table 1. parameter min typ max unit test conditions/comments ref in characteristics input frequency 10 300 mhz for f < 10 mhz, ensure slew rate > 21 v/s 10 30 mhz reference doubler enabled (db25 bit in register 2 is set to 1) input sensitivity 0.7 av dd v p-p biased at av dd /2; ac coupling ensures av dd /2 bias input capacitance 5.0 pf input current 60 a rf input characteristics for lower rf in frequencies, ensure slew rate > 400 v/s rf input frequency (rf in ) 0.5 3.0 ghz ?10 dbm rf input power +5 dbm prescaler output frequency 750 mhz phase detector phase detector frequency 26 mhz low noise mode 20 mhz low spur mode 26 mhz integer-n mode high voltage charge pump i cp sink/source high value 384 a r set = 5.1 k low value 48 a r set = 5.1 k r set range 3.3 10 k high value vs. r set 196 a r set = 10 k 594 a r set = 3.3 k sink and source current matching 6 % 1.0 v v cp (v p ? 1.0 v); v p = 6 v to 30 v absolute i cp accuracy 3 % i cp vs. v cp 2.5 % 1.0 v v cp (v p ? 1.0 v) i cp vs. temperature 2.5 % v cp = v p /2 i cp leakage 2.5 na v cp = v p /2 logic inputs input high voltage, v inh 2.0 v input low voltage, v inl 0.6 v input current, i inh /i inl 1 a input capacitance, c in 15.0 pf logic outputs output high voltage, v oh dv dd ? 0.4 v cmos output selected output high current, i oh 500 a output low voltage, v ol 0.4 v i ol = 500 a power supplies av dd 3.0 3.6 v dv dd , sdv dd av dd v v p 6.0 30 v set the v p supply at least 1 v above the maximum desired tuning voltage i p 1 2.5 ma v p = 30 v di dd + ai dd 1 50 60 ma current per output divider 6 to 24 ma ea ch output divide-by-2 consumes 6 ma typ i rfout 2 20 32 ma rf output stage is programmable low power sleep mode 1 a
adf4150hv rev. 0 | page 4 of 28 parameter min typ max unit test conditions/comments rf output characteristics output frequency using rf output dividers 31.25 mhz 500 mhz vco input and divide-by-16 selected harmonic content (second) ?19 dbc fundamental vco output ?20 dbc divided vco output harmonic content (third) ?13 dbc fundamental vco output ?10 dbc divided vco output minimum rf output power 2 ?4 dbm programmable in 3 db steps maximum rf output power 2 5 dbm programmable in 3 db steps output power variation vs. supply 1 db pull-up supply on pin 18 and pin 19 varied from 3.0 v to 3.6 v output power variation vs. temperature 1 db from ?40c to +85c level of signal with rf mute enabled ?37 dbm pdb rf pin brought low; rf = 2 ghz noise characteristics normalized in-band phase noise floor (pn synth ) 3 ?213 dbc/hz low noise mode ?203 dbc/hz low spur mode normalized 1/f noise (pn 1_f ) 4 ?113 dbc/hz low noise mode ?108 dbc/hz low spur mode rf output divider noise floor ?155 dbc/hz measured at 10 mhz offset spurious signals due to pfd frequency ?70 dbc at rf out +/rf out ? pins ?85 dbc at vco output 1 t a = 25c; av dd = dv dd = 3.3 v; prescaler = 8/9; f refin = 100 mhz; f pfd = 25 mhz; f rf = 1.75 ghz. 2 using 50 resistors to av dd , into a 50 load. 3 this figure can be used to calculate phase noise for any applic ation. to calculate in-band phase noise performance as seen at the vco output, use the following formula: pn synth = pn tot ? 10 log( f pfd ) ? 20 log n . 4 the pll phase noise is composed of flicker (1/f) noise plus the normalized pll noise floor. the flicker noise is specified at a 10 khz offset and normalized to 1 ghz. the formula for calculating the 1/f noise contribution at an rf frequency (f rf ) and at a frequency offset (f) is given by pn = pn 1_f + 10 log(10 khz/ f ) + 20 log( f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll .
adf4150hv rev. 0 | page 5 of 28 timing characteristics av dd = dv dd = sdv dd = 3.3 v 10%; v p = 6.0 v to 30 v; gnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85c. table 2. parameter limit unit description t 1 20 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 25 ns min clk high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width timing diagram clk data le le db31 (msb) db30 db1 (control bit c2) db2 (control bit c3) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 09058-002 figure 2. timing diagram
adf4150hv rev. 0 | page 6 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v p to gnd 1 ?0.3 v to +33 v digital i/o voltage to gnd 1 ?0.3 v to av dd + 0.3 v analog i/o voltage to gnd 1 ?0.3 v to dv dd + 0.3 v ref in to gnd 1 ?0.3 v to av dd + 0.3 v operating temperature range ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c reflow soldering peak temperature 260c time at peak temperature 40 sec 1 gnd = cp gnd = sd gnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. transistor count the transistor count for the adf4150hv is 23,380 (cmos) and 809 (bipolar). thermal resistance thermal impedance ( ja ) is specified for a device with the exposed pad soldered to gnd. table 4. thermal resistance package type ja unit 32-lead lfcsp (cp-32-11) 27.3 c/w esd caution
adf4150hv rev. 0 | page 7 of 28 pin configuration and fu nction descriptions 09058-003 24 gnd 23 gnd 22 dv dd 21 pdb rf 20 av dd 19 rf out + 18 rf out ? 17 gnd 1 2 3 4 5 6 7 8 gnd clk dat a le ce v p gnd gnd 9 10 11 12 13 14 15 16 cp out cp gnd av dd gnd av dd rf in + rf in ? gnd 32 31 30 29 28 27 26 25 gnd r set gnd sd gnd sdv dd muxout ld ref in adf4150hv top view (not to scale) notes 1. the lfcsp has an exposed pad that must be connected to gnd. figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1, 7, 8, 12, 16, 17, 23, 24, 30, 32 gnd ground. all ground pins should be tied together. 2 clk serial clock input. data is clocked in to the 32-bit shift register on the clk rising edge. this input is a high impedance cmos input. 3 data serial data input. the serial data is loaded msb first with the three lsbs as the control bits. this input is a high impedance cmos input. 4 le load enable. when le goes high, the data stored in th e 32-bit shift register is loaded into the register that is selected by the three control bits. this input is a high impedance cmos input. 5 ce chip enable. a logic low on this pin powers down the device and puts the charge pump into three-state mode. a logic high on this pin powers up the device. 6 v p high voltage charge pump power supply. place decoup ling capacitors to the ground plane as close to this pin as possible. the decoupling capacitors shou ld have the appropriate voltage rating (a value of 10 f is recommended). care should be taken to ensure that v p does not exceed the absolute maximum ratings on power-up (see table 3 ). a 10 series resistor can help to significantly reduce voltage overshoot with minimal ir drop. 9 cp out high voltage charge pump output. wh en enabled, this output provides i cp to the external passive loop filter. the output of the loop filter is connecte d to the voltage tuning port of the external vco. 10 cp gnd high voltage charge pump ground. all ground pins should be tied together. 11, 13, 20 av dd analog power supply. this pin ranges from 3.0 v to 3.6 v. place decoupling capacitors to the ground plane as close to this pin as possible. av dd must have the same value as dv dd . 14 rf in + positive rf input. the output of the vco or external prescaler should be ac-coupled to this pin. 15 rf in ? complementary rf input. if a single-ended input is re quired, this pin can be tied to ground via a 100 pf capacitor. 18 rf out ? divided-down output of rf in ?. this pin can be left unconnected if the divider functionality is not required. 19 rf out + divided-down output of rf in +. this pin can be left unconnected if the divider functionality is not required. 21 pdb rf rf power-down. a logic low on this pin mutes the rf outputs. this function is also software controllable. 22 dv dd digital power supply. place decoupling capacitors to the ground plane as close to this pin as possible. dv dd must have the same value as av dd . 25 ref in reference input. this cmos input has a nominal threshold of av dd /2 and a dc equivalent input resistance of 100 k. this input can be driven from a crystal oscillator, tcxo, or other reference. 26 ld lock detect output. a logic high output on this pin indicates pll lock. a logic low output indicates loss of pll lock.
adf4150hv rev. 0 | page 8 of 28 pin no. mnemonic description 27 muxout multiplexer output. the multiplexer output allows the lock detect, the n divider value, or the r counter value to be accessed externally. 28 sdv dd digital - modulator power supply. place decoupling capacitors to the ground plane as close to this pin as possible. sdv dd must have the same value as av dd . 29 sd gnd digital - modulator ground. all ground pins should be tied together. 31 r set connecting a resistor between this pin and gnd sets the charge pump output current. place the resistor as close to this pin as possible. the nominal voltage bias at the r set pin is 0.55 v. the relationship between i cp and r set is as follows: i cp = 1.96/ r set where: r set = 5.1 k. i cp = 384 a. ep exposed pad exposed pad. the lfcsp has an ex posed pad that must be connected to gnd.
adf4150hv rev. 0 | page 9 of 28 typical performance characteristics 0 2 4 6 8 101214161820222426 28 i cp (a) v cp (v) 09058-004 ?500 ?450 ?400 ?350 ?300 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 300 350 400 450 500 550 600 i cp = 50a source i cp = 50a sink i cp = 100a source i cp = 100a sink i cp = 150a source i cp = 150a sink i cp = 200a source i cp = 200a sink i cp = 250a source i cp = 250a sink i cp = 300a source i cp = 300a sink i cp = 350a source i cp = 350a sink i cp = 400a source i cp = 400a sink figure 4. charge pump output characteristics, v p = 28 v, i cp varied from 50 a to 400 a, r set = 5.1 k 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency (hz) 09058-005 ?170 ?165 ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 adf4150hv rms noise = 0.28 adf4156 rms noise = 0.36 figure 5. active filter phase noise, adf4150hv vs. adf4156 ; active filter implemented using op27 op amp; pfd = 20 mhz, loop bandwidth = 10 khz, i cp = 300 a, carrier frequency = 1.7 ghz, v p = 28 v 0 50 100 150 200 250 300 frequency (ghz) time (s) 09058-006 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.0 1.9 boost mode on boost mode off figure 6. pll lock time with boost mode on and off; locking over octave range jump (1 ghz to 2 ghz) for pfd = 20 mhz, loop bandwidth = 100 khz, i cp = 300 a, v p = 28 v, v dd = 3.3 v, ref in = 100 mhz 0 2 4 6 8 101214161820222426 28 i cp mismatch (%) v cp (v) 09058-007 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 16 v p = 6v mismatch (%) v p = 9v mismatch (%) v p = 12v mismatch (%) v p = 15v mismatch (%) v p = 18v mismatch (%) v p = 21v mismatch (%) v p = 24v mismatch (%) v p = 28v mismatch (%) figure 7. charge pump output mismatch vs. v p , i cp = 200 a 1500 1525 1520 1515 1510 1505 spur level (dbc) frequency (mhz) 09058-008 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 200khz 400khz 600khz 800khz beat note spur beat note spur figure 8. fractional spur levels vs. frequency, low spur mode; measured at vco output, pfd = 25 mhz, mod = 125 1500 1525 1520 1515 1510 1505 spur level (dbc) frequency (mhz) 09058-009 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 200khz 400khz 600khz 800khz figure 9. fractional spur levels vs. frequency, low noise mode; measured at vco output, pfd = 25 mhz, mod = 125
adf4150hv rev. 0 | page 10 of 28 1000 2000 1800 1600 1400 1200 spur level (dbc) frequency (mhz) 09058-110 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 25mhz 50mhz 75mhz 100mhz figure 10. pfd and reference spur le vels vs. frequency at vco output, ref in = 100 mhz, pfd = 25 mhz 1000 2000 1800 1600 1400 1200 spur level (dbc) frequency (mhz) 09058-111 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 25mhz 50mhz 75mhz 100mhz figure 11. pfd and reference spur le vels vs. frequency at vco output with adl5541 buffer placed between vco output and rf input, ref in = 100 mhz, pfd = 25 mhz 1000 1300 1250 1200 1150 1100 1050 phase noise (dbc/hz) frequency (mhz) 09058-112 ?110 ? 80 ?85 ?90 ?95 ?100 ?105 low noise mode low spur mode figure 12. in-band phase noise measured at 3 khz offset for low noise mode and low spur mode, pfd = 25 mhz, pll loop bandwidth = 40 khz 0 2500 2000 1500 1000 500 output power (dbm) frequency (mhz) 09058-113 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 +5dbm +2dbm ?1dbm ?4dbm figure 13. single-ended rf output power level vs. frequency and power setting, rf output pins pulled up to 3.3 v via 27 nh||50
adf4150hv rev. 0 | page 11 of 28 circuit description reference input section the reference input stage is shown in figure 14 . the sw1 and sw2 switches are normally closed. the sw3 switch is normally open. when power-down is initiated, sw3 is closed, and sw1 and sw2 are opened. in this way, no loading of the ref in pin occurs during power-down. buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control 09058-010 figure 14. reference input stage rf n divider the rf n divider allows a division ratio in the pll feedback path. the division ratio is determined by the int, frac, and mod values, which build up this divider (see figure 15 ). third-order fractional interpolator frac value mod value int value rf n divider n = int + frac/mod from vco output/ o utput dividers to pfd n counter 09058-011 figure 15. rf n divider int, frac, mod, and r counter relationship the int, frac, and mod values, in conjunction with the r counter, make it possible to generate output frequencies that are spaced by fractions of the pfd frequency. for more informa- tion, see the rf synthesizera worked example section. the rf vco frequency (rf out ) equation is rf out = ( f pfd / rf divider ) [ int + ( frac / mod )] (1) where: rf out is the output frequency of the external voltage controlled oscillator (vco). rf divider is the output divider that divides down the vco frequency. int is the preset divide ratio of the binary 16-bit counter (23 to 32,767 for the 4/5 prescaler, 75 to 65,535 for the 8/9 prescaler). frac is the numerator of the fractional division (0 to mod ? 1). mod is the preset fractional modulus (2 to 4095). the pfd frequency (f pfd ) equation is f pfd = ref in [(1 + d )/( r (1 + t ))] (2) where: ref in is the reference input frequency. d is the ref in doubler bit. r is the preset divide ratio of the binary 10-bit programmable reference counter (1 to 1023). t is the ref in divide-by-2 bit (0 or 1). integer-n mode if frac = 0 and the db8 (ldf) bit in register 2 is set to 1, the synthesizer operates in integer-n mode. the db8 bit in register 2 should be set to 1 for integer-n digital lock detect. r counter the 10-bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 1023 are allowed. phase frequency detector (pfd) and high voltage charge pump the phase frequency detector (pfd) takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 16 is a simplified schematic of the phase frequency detector. u3 clr2 q2 d2 u2 down up high high cp out ?in +in charge pump delay clr1 q1 d1 u1 09058-012 figure 16. pfd simplified schematic the pfd includes a delay element that sets the width of the antibacklash pulse to 4.2 ns. this pulse ensures that there is no dead zone in the pfd transfer function and provides a consistent reference spur level. the high voltage charge pump is designed on an analog devices, inc., proprietary high voltage process and allows the charge pump to output voltages as high as 29 v when powered by a 30 v supply. the high voltage charge pump removes the need for active filtering when interfacing to a high voltage vco.
adf4150hv rev. 0 | page 12 of 28 muxout and lock detect the multiplexer output on the adf4150hv allows the user to access various internal points on the chip. the state of muxout is controlled by the m3, m2, and m1 bits in register 2 (see figure 22). figure 17 shows the muxout section in block diagram form. gnd dv dd control mux muxout analog lock detect digital lock detect r counter output n counter output gnd reserved three-state-output dv dd r counter input 09058-013 figure 17. muxout schematic input shift registers the adf4150hv digital section includes a 10-bit rf r counter, a 16-bit rf n counter, a 12-bit frac counter, and a 12-bit modulus counter. data is clocked into the 32-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of six latches on the rising edge of le. the destination latch is determined by the state of the three control bits (c3, c2, and c1) in the shift register. as shown in figure 2, the control bits are the three lsbs: db2, db1, and db0. the truth table for these bits is shown in table 6. figure 19 summarizes how the latches are programmed. table 6. truth table for c3, c2, and c1 control bits control bits register c3 c2 c1 0 0 0 register 0 (r0) 0 0 1 register 1 (r1) 0 1 0 register 2 (r2) 0 1 1 register 3 (r3) 1 0 0 register 4 (r4) 1 0 1 register 5 (r5) program modes table 6 and figure 19 through figure 25 show how the program modes are set up in the adf4150hv . the following settings in the adf4150hv are double buffered: phase value, modulus value, reference doubler, reference divide- by-2, r counter value, and charge pump current setting. before the part uses a new value for any double-buffered setting, the following two events must occur: 1. the new value is latched into the device by writing to the appropriate register. 2. a new write is performed on register 0 (r0). for example, any time that the modulus value is updated, register 0 (r0) must be written to, to ensure that the modulus value is loaded correctly. the divider select value in register 4 (r4) is also double buffered, but only if the db13 bit of register 2 (r2) is high. output stage the rf out + and rf out ? pins of the adf4150hv are connected to the collectors of an npn differential pair driven by buffered outputs of the vco, as shown in figure 18. to allow the user to optimize the power dissipation vs. output power requirements, the tail current of the differential pair is programmable using bits[db4:db3] in register 4 (r4). four current levels can be set. these levels give output power levels of ?4 dbm, ?1 dbm, +2 dbm, and +5 dbm, respectively, using a 50 resistor to av dd and ac coupling into a 50 load. alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180 microstrip coupler (see the output matching section). if the outputs are used individually, the optimum output stage consists of a shunt inductor to av dd . vco rf out +rf out ? 09058-014 buffer/ divide-by-1/-2/-4/-8/-16 figure 18. output stage another feature of the adf4150hv is that the supply current to the rf output stage can be shut down until the part achieves lock, as measured by the digital lock detect circuitry. this feature is enabled by the mute-till-lock detect (mtld) bit in register 4 (r4).
adf4150hv rev. 0 | page 13 of 28 register maps db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0000pr1p12p11p10p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 d1 0 cp3 cp2 cp1 u6 u5 1 u3 u2 u1 c3(0) c2(1) c1(0) boost en rdiv2 reference doubler charge pump current setting 10-bit r counter control bits db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 b1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value ldp reserved power-down cp three- state counter reset output power clk div mode dbr 1 1 dbr = double buffered register?buffered by the write to register 0. 2 dbb = double buffered bits?buffered by the write to register 0, if and only if db13 of register 2 is high. reserved ldf reserved register 4 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d13 d12 d11 d10 0 0 0 0 0 0000000 0 d8 d3 d2 d1 c3(1) c2(0) c1(0) control bits reserved reserved rf output enable ld pin mode mtld divider select feedback select register 0 register 1 register 2 register 3 register 5 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 abp2 abp1 ce1 1 0 0 0 0 d15 d14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(1) control bits reserved reserved dbb 2 double buffer reserved reserved reserved dbr 1 dbr 1 dbr 1 dbr 1 dbr 1 reserved cc enable abp width reserved prescaler low noise and low spur modes muxout 09058-015 figure 19. regi ster summary
adf4150hv rev. 0 | page 14 of 28 n16 n15 ... n5 n4 n3 n2 n1 integer value (int) 00...00000 notallowed 00...00001 notallowed 00...00010 notallowed .......... ... 00...10110 notallowed 00...10111 23 00...11000 24 .......... ... 11...11101 65,533 11...11110 65,534 11...11111 65,535 f12 f11 ... f2 f1 fractional value (frac) 00...00 0 00...01 1 00...10 2 00...11 3 ....... . ....... . ....... . 1 1 ... 0 0 4092 1 1 ... 0 1 4093 1 1 ... 1 0 4094 1 1 ... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) intmin = 75 with prescaler = 8/9 09058-016 figure 20. register 0 (r0) p12 p11 ... p2 p1 phase value (phase) 0 0 ... 0 0 0 0 0 ... 0 1 1 (recommended) 0 0 ... 1 0 2 0 0 ... 1 1 3 . . ... . . . . . ... . . . . . ... . . . 1 1 ... 0 0 4092 1 1 ... 0 1 4093 1 1 ... 1 0 4094 1 1 ... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0000pr1p12p11p10p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) reserved m12 m11 ... ... ... ... ... ... ... ... ... ... m2 m1 interpolator modulus (mod) 00 102 00 113 .. ... .. ... .. ... 1 1 0 0 4092 1 1 0 1 4093 1 1 1 0 4094 1 1 1 1 4095 prescaler p1 prescaler 04/5 18/9 dbr dbr 09058-017 figure 21. register 1 (r1)
adf4150hv rev. 0 | page 15 of 28 rd2 reference doubler 0disabled 1enabled rd1 reference divide-b y-2 0 disabled 1 enabled cp3 cp2 cp1 i cp (a) 5.1k ? 00048 00196 010144 011192 100240 101288 110336 111384 r10 r9 ... ... ... ... ... ... ... ... ... ... r2 r1 r counter (r) 00 011 00 102 .. ... .. ... .. ... 1 1 0 0 1020 1 1 0 1 1021 1 1 1 0 1022 1 1 1 1 1023 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 d1 0 cp3 cp2 cp1 u6 u5 1 u3 u2 u1 c3(0) c2(1) c1(0) rdiv2 dbr reference doubler dbr charge pump current setting 10-bit r counter dbr control bits ldp reserved power-down cp three- state counter reset ldf muxout double buffer reserved u5 ldp 010ns 16ns reserved bit 0 reserved 1normal operation u3 power-down 0disabled 1enabled u2 cp three-state 0disabled 1enabled u1 counter reset 0disabled 1enabled d1 double buffer r4[db22:db20] 0disabled 1 enabled u6 ldf 0frac-n 1int-n reserved m3 m2 m1 output 0 0 0 three-state output 00 1dv dd 01 0gnd 0 1 1 r counter output 1 0 0 n divider output 1 0 1 analog lock detect 1 1 0 digital lock detect 1 1 1 reserved l2 l1 noise mode 00lownoisemode 0 1 reserved 1 0 reserved 11lowspurmode low noise and low spur modes 09058-018 dbr figure 22. register 2 (r2) c 2 c 1 clock divider mode 0 0 clock divider off 0 1 reserved 1 0 resync enable 1 1 reserved d12 d11 ... d2 d1 clock divider value 00...00 0 00...01 1 00...10 2 00...11 3 ....... . ....... . ....... . 1 1 ... 0 0 4092 1 1 ... 0 1 4093 1 1 ... 1 0 4094 1 1 ... 1 1 4095 boost en db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 b1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value clk div mode reserved b1 boost enable 0 disabled 1 enabled reserved 0 0 00 09058-019 figure 23. register 3 (r3)
adf4150hv rev. 0 | page 16 of 28 d3 rf out 0 disabled 1 enabled d2 d1 output power (dbm) 00?4 01?1 10+2 11+5 d8 mute till lock detect 0 mute disabled 1 mute enabled d12 d11 rf divider select 00 1 00 2 01 4 01 8 d10 0 1 0 1 10 16 0 d13 feedback select 0 fundamental 1 divided output power db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d13 d12 d11 d10 0 0 0 0 0 0 0 0 0 d8 0 0 0 0 d3 d2 d1 c3(1) c2(0) c1(0) control bits reserved reserved rf output enable mtld divider select feedback select reserved dbb 09058-020 figure 24. register 4 (r4) ld pin mode db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 abp2abp1ce110000d15d140000000000000000000c3(1)c2(0)c1(1) control bits reserved reserved reserved cc enable abp width d15 d14 lock detect pin operation 0 0 output low 0 1 digital lock detect 1 1 0 output low 11output high abp2 abp1 antibacklash pulse width 0 0 4.2ns (recommended) 0 1 reserved 1 0 reserved 1 1 reserved reserved bit 0 reserved 1 normal operation ce1 charge cancell ation 1 muxout in register 2 must also be set to digital lock detect for the lock detect pin to operate correctly. 0disabled 1 enabled 09058-021 figure 25. register 5 (r5)
adf4150hv rev. 0 | page 17 of 28 register 0 control bits when bits[c3:c1] are set to 000, register 0 is programmed. figure 20 shows the input data format for programming this register. 16-bit integer value (int) the 16 int bits (bits[db30:db15]) set the int value, which determines the integer part of the feedback division factor. the int value is used in equation 1 (see the int, frac, mod, and r counter relationship section). integer values from 23 to 32,767 are allowed for the 4/5 prescaler; for the 8/9 prescaler, the minimum integer value is 75 and the maximum value is 65,535. 12-bit fractional value (frac) the 12 frac bits (bits[db14:db3]) set the numerator of the fraction that is input to the - modulator. this fraction, along with the int value, specifies the new frequency channel that the synthesizer locks to, as shown in the rf synthesizera worke d e x ampl e section. frac values from 0 to (mod ? 1) cover channels over a frequency range equal to the pfd refer- ence frequency. register 1 control bits when bits[c3:c1] are set to 001, register 1 is programmed. figure 21 shows the input data format for programming this register. prescaler value the dual-modulus prescaler, along with the int, frac, and mod values, determines the overall division ratio from the vco output to the pfd input. the pr1 bit (db27) in register 1 sets the prescaler value. operating at cml levels, the prescaler takes the clock from the vco output and divides it down for the counters. the prescaler is based on a synchronous 4/5 core. when the prescaler is set to 4/5, the maximum rf frequency allowed is 3 ghz. therefore, when operating the adf4150hv above 3 ghz, the prescaler must be set to 8/9. the prescaler limits the int value as follows: ? prescaler = 4/5: n min = 23 ? prescaler = 8/9: n min = 75 12-bit phase value bits[db26:db15] control the phase word. the word must be less than the mod value programmed in register 1. the phase word is used to program the rf output phase from 0 to 360 with a resolution of 360/mod. for more information, see the phase resync section. in most applications, the phase relationship between the rf signal and the reference is not important. in such applications, the phase value can be used to optimize the fractional and subfractional spur levels. for more information, see the spur consistency and fractional spur optimization section. if neither the phase resync nor the spurious optimization function is used, it is recommended that the phase word be set to 1. 12-bit modulus value (mod) the 12 mod bits (bits[db14:db3]) set the fractional modulus. the fractional modulus is the ratio of the pfd frequency to the channel step resolution on the rf output. for more information, see the 12-bit programmable modulus section. register 2 control bits when bits[c3:c1] are set to 010, register 2 is programmed. figure 22 shows the input data format for programming this register. low noise and low spur modes the noise modes on the adf4150hv are controlled by setting bits[db30:db29] in register 2 (see figure 22 ). the noise modes allow the user to optimize a design either for improved spurious performance or for improved phase noise performance. when the low spur mode is chosen, dither is enabled. dither randomizes the fractional quantization noise so that it resembles white noise rather than spurious noise. as a result, the part is optimized for improved spurious performance. low spur mode is normally used for fast-locking applications when the pll closed-loop bandwidth is wide. wide loop bandwidth is a loop bandwidth greater than 1/10 of the rf out channel step resolu- tion (f res ). a wide loop filter does not attenuate the spurs to the same level as a narrow loop bandwidth. for best noise performance, use the low noise mode option. when the low noise mode is chosen, dither is disabled. this mode ensures that the charge pump operates in an optimum region for noise performance. low noise mode is extremely useful when a narrow loop filter bandwidth is available. the synthesizer ensures extremely low noise, and the filter attenu- ates the spurs. figure 8 and figure 9 show fractional spur levels when using low spur mode and low noise mode. figure 12 shows the in-band phase noise when using low spur mode and low noise mode. muxout the on-chip multiplexer is controlled by bits[db28:db26] (see figure 22 ).
adf4150hv rev. 0 | page 18 of 28 reference doubler setting the db25 bit to 0 disables the doubler and feeds the ref in signal directly into the 10-bit r counter. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding it into the 10-bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and the low spur mode is chosen, the in-band phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cycle in the low noise mode and when the doubler is disabled. the maximum allowable ref in frequency when the doubler is enabled is 30 mhz. rdiv2 setting the db24 bit to 1 inserts a divide-by-2 toggle flip-flop between the r counter and the pfd. this function allows a 50% duty cycle signal to appear at the pfd input, which is necessary when the charge pump boost mode is enabled (see the boost enable section). 10-bit r counter the 10-bit r counter (bits[db23:db14]) allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 1023 are allowed. double buffer the db13 bit enables or disables double buffering of bits[db22:db20] in register 4. for information about how double buffering works, see the program modes section. charge pump current setting bits[db11:db9] set the charge pump current. this value should be set to the charge pump current that the loop filter is designed with (see figure 22). lock detect function (ldf) the db8 bit configures the lock detect function (ldf). the ldf controls the number of pfd cycles monitored by the lock detect circuit to ascertain whether lock has been achieved. when db8 is set to 0, the number of pfd cycles monitored is 40. when db8 is set to 1, the number of pfd cycles monitored is 5. it is recommended that the db8 bit be set to 0 for fractional-n mode and 1 for integer-n mode. lock detect precision (ldp) the lock detect precision bit (bit db7) sets the comparison window in the lock detect circuit. when db7 is set to 0, the comparison window is 10 ns; when db7 is set to 1, the window is 6 ns. the lock detect circuit goes high when n consecutive pfd cycles are less than the comparison window value; n is set by the ldf bit (db8). for example, with db8 = 0 and db7 = 0, 40 consecutive pfd cycles of 10 ns or less must occur before digital lock detect goes high. the recommended settings for bits[db8:db7] are listed in table 7. table 7. recommended ldf and ldp bit settings mode db8 (ldf) db7 (ldp) integer-n 1 1 fractional-n, low noise mode 0 1 fractional-n, low spur mode 0 0 power-down (pd) the db5 bit provides the programmable power-down mode. setting this bit to 1 performs a power-down. setting this bit to 0 returns the synthesizer to normal operation. in software power- down mode, the part retains all information in its registers. the register contents are lost only if the supply voltages are removed. when power-down is activated, the following events occur: ? synthesizer counters are forced to their load state conditions. ? charge pump is forced into three-state mode. ? digital lock detect circuitry is reset. ? rf out buffers are disabled. ? input registers remain active and capable of loading and latching data. charge pump three-state setting the db4 bit to 1 puts the charge pump into three-state mode. this bit should be set to 0 for normal operation. counter reset the db3 bit is the reset bit for the r counter and the n counter of the adf4150hv . when this bit is set to 1, the rf synthesizer n counter and r counter are held in reset. for normal opera- tion, this bit should be set to 0.
adf4150hv rev. 0 | page 19 of 28 register 3 control bits when bits[c3:c1] are set to 011, register 3 is programmed. figure 23 shows the input data format for programming this register. boost enable setting the db18 bit to 1 enables the charge pump boost mode. if boost mode is enabled, the narrow loop bandwidth is main- tained for spur attenuation, but faster lock times are still possible. boost mode speeds up locking significantly for higher values of pfd frequencies that normally have many cycle slips. when boost mode is enabled, an extra charge pump current cell is turned on. this cell outputs a constant current to the loop filter or removes a constant current from the loop filter (depending on whether the vco tuning voltage needs to increase or decrease to acquire the new frequency) until v tune approaches the lock voltage. the boost current is then disabled and the charge pump current setting reverts to the user programmed value. loop stability is maintained because the current is constant and is not pulsed, so there is no need to switch a compensating loop filter resistor in and out, as in standard fast lock modes. note that the pfd requires a 45% to 55% duty cycle for the boost mode to operate correctly. this duty cycle can be guaranteed by setting the rdiv2 bit (db24) in register 2. clock divider mode bits[db16:db15] must be set to 10 to activate phase resync (see the phase resync section). setting bits[db16:db15] to 00 disables the clock divider (see figure 23 ). 12-bit clock divider value bits[db14:db3] set the 12-bit clock divider value. this value is the timeout counter for activation of phase resync. for more information, see the phase resync section. register 4 control bits when bits[c3:c1] are set to 100, register 4 is programmed. figure 24 shows the input data format for programming this register. feedback select the db23 bit selects the feedback from the vco output to the n counter. when this bit is set to 1, the signal is taken directly from the vco. when this bit is set to 0, the signal is taken from the output of the output dividers. the dividers enable coverage of the wide frequency band (31.25 mhz to 3.0 ghz). when the dividers are enabled and the feedback signal is taken from the output, the rf output signals of two separately configured plls are in phase. this is useful in some applications where the posi- tive interference of signals is required to increase the power. divider select bits[db22:db20] select the value of the output divider (see figure 24 ). mute-till-lock detect (mtld) when the db10 bit is set to 1, the supply current to the rf output stage is shut down until the part achieves lock, as measured by the digital lock detect circuitry. rf output enable the db5 bit enables or disables the primary rf output. if db5 is set to 0, the primary rf output is disabled; if db5 is set to 1, the primary rf output is enabled. output power bits[db4:db3] set the value of the primary rf output power level (see figure 24 ). register 5 control bits when bits[c3:c1] are set to 101, register 5 is programmed. figure 25 shows the input data format for programming this register. antibacklash pulse width bits[db31:db30] set the pfd antibacklash pulse width. the recommended value for all operating modes is 4.2 ns (set bits[db31:db30] to 00). other antibacklash pulse width settings are reserved and are not recommended. charge cancellation setting the db29 bit to 1 enables charge pump charge cancel- lation. this has the effect of reducing pfd spurs in integer-n mode. in fractional-n mode, this bit should be set to 0. lock detect pin operation bits[db23:db22] set the operation of the lock detect (ld) pin (see figure 25 ). register initialization sequence at initial power-up, after the correct application of voltages to the supply pins, the adf4150hv registers should be started in the following sequence: 1. register 5 2. register 4 3. register 3 4. register 2 5. register 1 6. register 0
adf4150hv rev. 0 | page 20 of 28 rf synthesizera worked example the following equations are used to program the adf4150hv synthesizer: rf out = [ int + ( frac / mod )] ( f pfd / rf divider) (3) where: rf out is the rf frequency output. int is the integer division factor. frac is the fractionality. mod is the modulus. rf divider is the output divider that divides down the vco frequency. f pfd = ref in [(1 + d )/( r (1 + t ))] (4) where: ref in is the reference frequency input. d is the rf ref in doubler bit (0 or 1). r is the rf reference division factor (1 to 1023). t is the reference divide-by-2 bit (0 or 1). in this example, the user wants to program a 1.5 ghz rf frequency output (rf out ) with a 500 khz channel resolution (f resout ) required on the rf output. the reference frequency input (ref in ) is 25 mhz. the vco options available to the user include the following: ? 1.5 ghz vco in fundamental mode ? 3 ghz vco with the rf divider set to 2 when enabling the rf divider, the user must decide whether to close the pll loop before the rf divider or after it. in this example, the pll loop is closed before the rf divider (see figure 26 ). f pfd pfd vco n divider 2 rf out 09058-022 figure 26. pll loop closed before output divider to minimize vco feedthrough, the 3 ghz vco is selected. a channel resolution (f resout ) of 500 khz is required at the output of the rf divider. therefore, the channel resolution at the output of the vco (f res ) needs to be 2 f resout , that is, 1 mhz. mod = ref in / f res mod = 25 mhz/1 mhz = 25 from equation 4, f pfd = [25 mhz (1 + 0)/1] = 25 mhz (5) 1500.5 mhz = 25 mhz [( int + ( frac /25))/2] (6) where: int = 120. frac = 1. rf divider = 2. the adf4150hv evaluation software can be used to help determine integer and fractional values for a given setup, along with the actual register settings to be programmed. reference doubler an d reference divider the on-chip reference doubler allows the input reference signal to be doubled. doubling the reference signal doubles the pfd comparison frequency, which improves the noise performance of the system. doubling the pfd frequency usually improves noise performance by 3 db. note that the pfd cannot operate above 32 mhz due to a limitation in the speed of the - circuit of the n divider. the reference divide-by-2 divides the reference signal by 2, resulting in a 50% duty cycle pfd frequency. this is necessary for the correct operation of the charge pump boost mode. for more information, see the boost enable section. 12-bit programmable modulus the choice of modulus (mod) depends on the reference signal (ref in ) available and the channel resolution (f res ) required at the rf output. for example, a gsm system with 13 mhz ref in sets the modulus to 65. this means that the rf output resolution (f res ) is the 200 khz (13 mhz/65) necessary for gsm. with dither off, the fractional spur interval depends on the modulus values chosen (see table 8 ). unlike most other fractional-n plls, the adf4150hv allows the user to program the modulus over a 12-bit range. when combined with the reference doubler and the 10-bit r counter, the 12-bit modulus allows the user to set up the part in many different configurations for the application. for example, consider an application that requires a 1.75 ghz rf frequency output with a 200 khz channel step resolution. the system has a 13 mhz reference signal. one possible setup is to feed the 13 mhz reference signal directly into the pfd and to program the modulus to divide by 65. this setup results in the required 200 khz resolution. another possible setup is to use the reference doubler to create 26 mhz from the 13 mhz input signal. the 26 mhz is then fed into the pfd, and the modulus is programmed to divide by 130. this setup also results in 200 khz resolution but offers superior phase noise performance over the first setup. the programmable modulus is also very useful for multistandard applications with different channel spacing requirements. it is important that the pfd frequency remain constant (in this example, 13 mhz). this allows the user to design one loop filter for both setups without encountering stability issues. note that the ratio of the rf frequency to the pfd frequency principally affects the loop filter design, not the actual channel spacing.
adf4150hv rev. 0 | page 21 of 28 spurious optimization and boost mode narrow loop bandwidths can filter unwanted spurious signals, but these bandwidths usually have a long lock time. a wider loop bandwidth achieves faster lock times, but may lead to increased spurious signals inside the loop bandwidth. the boost mode feature can achieve the same fast lock time as the wider bandwidth, but with the advantage of a narrow final loop bandwidth to keep spurs low (see the boost enable section). spur mechanisms this section describes the three different spur mechanisms that arise with a fractional-n synthesizer and how to minimize them in the adf4150hv . fractional spurs the fractional interpolator in the adf4150hv is a third-order - modulator with a modulus (mod) that is programmable to any integer value from 2 to 4095. in low spur mode (dither on), the minimum allowable value of mod is 50. the - modulator is clocked at the pfd reference rate (f pfd ), which allows pll out- put frequencies to be synthesized at a channel step resolution of f pfd /mod. in low noise mode (dither off), the quantization noise from the - modulator appears as fractional spurs. the interval between spurs is f pfd /l, where l is the repeat length of the code sequence in the digital - modulator. for the third-order - modulator used in the adf4150hv , the repeat length depends on the value of mod, as listed in table 8. table 8. fractional spurs with dither off (low noise mode) mod value (dither off) repeat length spur interval mod is divisible by 2, but not by 3 2 mod channel step/2 mod is divisible by 3, but not by 2 3 mod channel step/3 mod is divisible by 6 6 mod channel step/6 mod is not divisible by 2, 3, or 6 mod channel step in low spur mode (dither on), the repeat length is extended to 2 21 cycles, regardless of the value of mod, which makes the quantization error spectrum look like broadband noise. this may degrade the in-band phase noise at the pll output by as much as 10 db. for lowest noise, dither off is a better choice, particularly when the final loop bandwidth is low enough to attenuate even the lowest frequency fractional spur. integer boundary spurs another mechanism for fractional spur creation is the inter- actions between the rf vco frequency and the reference frequency. when these frequencies are not integer related (the purpose of a fractional-n synthesizer), spur sidebands appear on the vco output spectrum at an offset frequency that corre- sponds to the beat note, or difference frequency, between an integer multiple of the reference and the vco frequency. these spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth (thus the name integer boundary spurs). reference spurs reference spurs are generally not a problem in fractional-n synthesizers because the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechanism that bypasses the loop may cause a problem. the pcb layout must ensure adequate isolation between vco traces and the input reference to avoid a possible feedthrough path on the board. spur consistency and fractional spur optimization with dither off, the fractional spur pattern due to the quantiza- tion noise of the - modulator also depends on the particular phase word with which the modulator is seeded. the phase word can be varied to optimize the fractional and subfractional spur levels on any particular frequency. thus, a lookup table of phase values corresponding to each frequency can be constructed for use when programming the adf4150hv . if a lookup table is not used, keep the phase word at a constant value to ensure consistent spur levels on any particular frequency.
adf4150hv rev. 0 | page 22 of 28 phase resync in the example shown in figure 27 , the pfd reference is 25 mhz and mod is 125 for a 200 khz channel spacing. t sync is set to 400 s by programming clk_div_value = 80. the output of a fractional-n pll can settle to any one of the mod phase offsets with respect to the input reference, where mod is the fractional modulus. the phase resync feature of the adf4150hv produces a consistent output phase offset with respect to the input reference. this is necessary in applications where the output phase and frequency are important, such as digital beamforming. for information about how to program a specific rf output phase when using phase resync, see the phase programmability section. le phase frequency sync (internal) ?100 0 100 200 1000 300 400 500 600 700 800 900 time (s) pll settles to correct phase after resync t sync last cycle slip pll settles to incorrect phase 09058-025 phase resync is enabled by setting bits[db16:db15] in register 3 to 10. when phase resync is enabled, an internal timer generates sync signals at intervals of t sync given by the following formula: t sync = clk_div_value mod t pfd where: clk_div_value is the decimal value programmed in bits[db14:db3] of register 3 and can be any integer in the range of 1 to 4095. mod is the modulus value programmed in bits[db14:db3] of register 1. t pfd is the pfd reference period. figure 27. phase resync example phase programmability the phase word in register 1 controls the rf output phase. as this word is swept from 0 to mod, the rf output phase sweeps over a 360 range in steps of 360/mod. when a new frequency is programmed, the second sync pulse after the le rising edge is used to resynchronize the output phase to the reference. the t sync time must be programmed to a value that is at least as long as the worst-case lock time. this guarantees that the phase resync occurs after the last cycle slip in the pll settling transient.
adf4150hv rev. 0 | page 23 of 28 applications information ultrawideband pll when paired with an octave tuning range vco, the adf4150hv provides an ultrawideband pll function using the on-board rf dividers. with an octave tuning range at the fundamental frequency, the rf dividers provide full frequency coverage with no gaps down to much lower frequencies. for example, using a 1 ghz to 2 ghz octave range vco (such as the synergy dcys100200-12), the user can obtain contiguous output frequencies from 62.5 mhz to 2 ghz at the adf4150hv rf outputs, as shown in figure 28 . a broadband output match is achieved using a 27 nh inductor in parallel with a 50 resistor (for more information, see the output matching section). with such a wide output range, the same pll hardware design can generate different frequencies for each of the different hardware platforms in the system. microwave pll the adf4150hv can be interfaced directly to a wide tuning range microwave vco without the need for an active filter. typically, most microwave vcos have a maximum tuning range of 15 v. in this case, set v p on the adf4150hv to a value of 16 v or higher to ensure sufficient headroom in the charge pump. an external prescaler, such as the adf5001 , is required to divide down vco frequencies that are above the maximum rf input frequency of 3.0 ghz. in the application circuit shown in figure 29 , the adf5001 divides down the 16 ghz vco signal to 4 ghz, which can then be input directly into the adf4150hv rf inputs. the adf5001 can be connected either single-ended or differentially to the adf4150hv . for best performance and to achieve maximum power transfer, it is recommended that a differential connection be used. rfout vtune 150? 150? synergy dcys100200-12 octave range vco rf in + rf out ? rf out + rf in ? cp out adf4150hv pll 37? z bias = 50? ||27nh z bias v dd rf out = 62.5mhz to 2ghz 09058-026 figure 28. ultrawideband pll using the adf4150hv and an octave tuning range vco
adf4150hv rev. 0 | page 24 of 28 rfout vtune 150? 150 ? 18 ? microwave vco cp out adf4150hv pll 37 ? 6db pad 18? rfout rfout rfin gnd vdd2 vdd1 adf5001 prescaler 0.1f 10pf 16ghz out ac coupling integrated on adf5001 device 09058-027 rf in + rf in ? 18? figure 29. 16 ghz microwave pll generating the high voltage supply it is possible to use a boost con verter such as the analog devices adp1613 to generate the high voltage charge pump supply from a lower voltage rail without degrading pll performance. to minimize any switching noise feedthrough, ensure that sufficient decoupling is placed close to the charge pump supply pin (pin 6). care should be taken to use capacitors with the appropriate voltage rating; for example, if using a boost converter to generate a 20 v v p supply, use capacitors with a rating of 20 v or higher. the design of the boost converter is simplified using the adp161x excel-based design tool. this tool is available from the adp1613 product page . figure 30 shows the user inputs for an example 5 v input to 20 v output design. to minimize voltage ripple at the output of the converter stage, the noise filter option is selected, and the vout r ippl e field is set to its minimum value. the high voltage charge pump current draw is 2 ma maximum; therefore, a value of 10 ma is entered in the iout field to provide margin. when tested with the adf4150hv evaluation board, this design showed no evident switching spurs at the vco output. 09058-028 figure 30. adp161x designer tool
adf4150hv rev. 0 | page 25 of 28 interfacing to the aduc702x and the adsp-bf527 the adf4150hv has a simple spi-compatible serial interface for writing to the device. the clk, data, and le pins control the data transfer. when le goes high, the 32 bits that were clocked into the appropriate register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 6 for the register address table. aduc702x interface figure 31 shows the interface between the adf4150hv and the aduc702x family of analog microcontrollers. the aduc702x family is based on an arm7 core, but the same interface can be used with any 8051-based microcontroller. the microcontroller is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4150hv needs a 32-bit word, which is accomplished by writing four 8-bit bytes from the micro- controller to the device. after the fourth byte is written, the le input should be brought high to complete the transfer. aduc702x adf4150hv clk data le ce muxout (lock detect) sclock mosi i/o ports 09058-030 figure 31. aduc702x to adf4150hv interface i/o port lines on the aduc702x are also used to control the power-down input (ce) and the lock detect (muxout con- figured for lock detect and polled by the port input). when operating in the mode described, the maximum spi transfer rate of the aduc7023 is 20 mbps. this means that the maxi- mum rate at which the output frequency can be changed is 833 khz. if using a faster spi clock, make sure that the spi timing requirements listed in table 2 are adhered to. blackfin adsp-bf527 interface figure 32 shows the interface between the adf4150hv and the black fin ? adsp-bf527 digital signal processor (dsp). the adf4150hv needs a 32-bit serial word for each latch write. the easiest way to accomplish this using the black fin family is to use the autobuffered transmit mode of operation with alternate framing. this mode provides a means for transmitting an entire block of serial data before an interrupt is generated. adsp-bf527 adf4150hv clk data le ce muxout (lock detect) sck mosi gpio i/o ports 09058-031 figure 32. adsp-bf527 to adf4150hv interface set up the word length for eight bits and use four memory loca- tions for each 32-bit word. to program each 32-bit latch, store the 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. if using a faster spi clock, make sure that the spi timing requirements listed in table 2 are adhered to. pcb design guidelines for a chip scale package the lands on the chip scale package (cp-32-11) are rectangular. the pcb pad for these lands must be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. each land must be centered on the pad to ensure that the solder joint size is maximized. the bottom of the chip scale package has a central exposed thermal pad. the thermal pad on the pcb must be at least as large as the exposed pad. on the pcb, there must be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, they must be incorporated into the thermal pad at 1.2 mm pitch grid. the via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with 1 oz. of copper to plug the via.
adf4150hv rev. 0 | page 26 of 28 output matching the circuit shown in figure 34 provides a good broadband match to 50 for frequencies from 250 mhz to 3.0 ghz. the maximum output power in this case is approximately 5 dbm. the inductor can be increased for operation below 250 mhz. both single-ended architectures can be examined using the EVAL-ADF4150HVEB1Z evaluation board. the output of the adf4150hv can be matched in a number of ways for optimum operation; the most basic is to connect a 50 resistor to av dd . a dc bypass capacitor of 100 pf is connected in series, as shown in figure 33 . because the resistor is not fre- quency dependent, this method provides a good broadband match. when connected to a 50 load, this circuit typically gives a differential output power equal to the values chosen by bits[db4:db3] in register 4. 09058-032 22nh 1nf rf out + rf out ? a v dd av dd 50? 22nh 1nf 50 ? 100? 50? 50? 50 ? 100pf rf out a v dd 50? 09058-029 figure 33. simple adf4150hv output stage another solution is to connect a shunt inductor (acting as an rf choke) to av dd . this solution can help provide a better narrow- band match and, therefore, more output power. however, because the output stage is open-collector, it is recommended that a termination resistor be used in addition to the rf choke to give a defined output impedance. the termination resistor can be either 50 in parallel with the rf choke or 100 connected across the rf output pins. figure 34. optimum adf4150hv output stage if differential outputs are not needed, the unused output can be terminated, or both outputs can be combined using a balun.
adf4150hv rev. 0 | page 27 of 28 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bottom view top view pin 1 indi c ator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.65 3.50 sq 3.45 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 35. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-11) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adf4150hvbcpz ?40c to +85c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-11 adf4150hvbcpz-rl7 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_wq] cp-32-11 EVAL-ADF4150HVEB1Z evaluation board 1 z = rohs compliant part.
adf4150hv rev. 0 | page 28 of 28 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09058-0-8/11(0)

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